This invention relates to a logical circuit of the CMOS type, having a large power voltage margin and a large noise margin.
For example, a circuit such as that shown in FIG. 1 is known as an inverter circuit in a conventional CMOS logical circuit. Thus, the source and drain of an n-channel MOS transistor 1 are interposed between a power voltage V.sub.ss and an output terminal V.sub.out. A p-channel MOS transistor 2 is interposed between the output terminal V.sub.out and the power voltage V.sub.cc. Both gates of each of the n and p-channel MOS transistors 1, 2 are commonly connected to an input terminal V.sub.in.
Assuming that a power voltage V.sub.cc is 5 V and another power voltage V.sub.ss is 0 V, when the input terminal V.sub.in is 0 V, transistor 1 is turned off and transistor 2 is turned on, so that the power voltage V.sub.cc of 5 V is output from the output terminal V.sub.out. Assuming that the input terminal V.sub.in is 5 V, transistor 1 is turned on and transistor 2 is turned off, a power voltage V.sub.ss of 0 V will be output from the output terminal V.sub.out.
In such an inverter circuit, a power voltage margin V.sub.margin is the absolute value of the difference between the maximum voltage value V.sub.ccmax to be determined by the breakdown voltage of the circuit and the minimum voltage value V.sub.ccmin at which the normal operation can be performed or, in other words EQU V.sub.margin =.vertline.V.sub.ccmax -V.sub.ccmin .vertline..
In the above equation, it is generally impossible to increase the maximum voltage V.sub.ccmax since, to do so, it would be necessary to change the structure of the transistor.
On the other hand, the minimum voltage value V.sub.ccmin and threshold voltages V.sub.thn, V.sub.thp must theoretically satisfy the conditions represented by the following inequality; EQU V.sub.ccmin &gt;max(.vertline.V.sub.thn .vertline., .vertline.V.sub.thp .vertline.).
Therefore, it is desirable to reduce the threshold voltages V.sub.thn, V.sub.thp of transistors 1 and 2 and to enlarge the power voltage margin V.sub.margin. However, the values of the threshold voltages V.sub.thn and V.sub.thp are generally set at about 1 V since, due to limitations of process manufacturing technology, they cannot be greatly reduced.
On the contrary, reduction of the threshold voltages V.sub.thn and V.sub.thp would cause the output to be easily inverted, due to a noise which exceeds these values, so that the noise margin would be decreased and a malfunction might easily occur.
In other words, since enlargement of the power voltage margin and enlargement of the noise margin are mutually opposite conditions, it would be extremely difficult to satisfy both simultaneously.